1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) and, in particular, to the technique for achieving a high density integration for memory cells.
2. Description of the Related Art
In the conventional DRAM memory cell, use has been made of a memory cell of one transistor and one capacitor. With a recent higher density integration of a semiconductor memory device, there is a growing demand for achieving more reduction of the memory cell's occupation area.
FIG. 1A is an equivalent circuit for a conventional memory cell, FIG. 1B is a view showing a planar layout of it and FIG. 1C shows a cross-section as taken along the line 1C—1C in FIG. 1B. As shown in FIGS. 1B and 1C, the occupation area of one memory cell is determined by one planar type transistor Q, one bit line contact 3 for two cells, storage node contact 4, passing word line 2′ and element isolation region 5. With a minimal work dimension given by F at the state of the art and each one side of the gate electrode and source/drain region given by F, the minimal occupation area of the memory cell becomes “2F in length×4F in width”=an area 8F2. In such an element configuration, it is not possible to reduce its dimension any more and hence to achieve the reduction of a resultant chip size. It is desired that, in order to obtain a low-cost DRAM, more size-reducible element configuration be adopted. It is to be noted that, in FIGS. 1A to 1C, reference numeral 1 shows a bit line; 2, a word line and 6, a plate electrode line.
Therefore, there is a need for providing a memory cell structure capable of reducing the occupation area of the memory cell down to 4F2 or below.